FPGA Reference Designs for Low-Latency Decode

Mechanism

Open reference RTL and bring-up notes for the synchronization fabric on commodity FPGA boards. Trinity (US Prov. 63/987,139) describes the async dual-port FIFO, hysteretic occupancy comparator, and sideband phase-correction signal architecture as a digital logic device; this research line is the implementation discipline that turns that architecture into a reproducible bring-up flow on commodity FPGA targets (Lattice CrossLink-NX, Xilinx Artix-7, Intel Cyclone-V class). The output is reference SystemVerilog plus characterization notes (timing-closure constraints, watermark calibration sweeps, sideband electrical layout), not a competing IP filing. The reference designs target multi-stream HDR pipelines where independently-clocked discrete decoder ICs feed a master compositor and scanline-granular fill monitoring across decoder boundaries is required.

Why this matters

• The Trinity architecture has a non-obvious bring-up path. Discrete decoder ICs with independent slave clocks need scanline-granular fill monitoring across decoder boundaries, which is the kind of thing that looks straightforward in the spec and takes a quarter of FPGA engineering time to actually close timing on. The published reference encodes that quarter into a starting point.
• Reference RTL on commodity boards lowers the integration cost for hardware partners and architecture-channel customers. It is a moat-adjacent investment, not a moat itself; the value is in shortening the partner-side evaluation cycle from a multi-month port to a weekend bring-up on an off-the-shelf evaluation kit.
• The work is research-status with no separate filing. The moat lives in the Trinity provisional. Reference RTL is published to lower partner integration friction, on the same logic as a vendor reference design accompanying a standard part, not as a competing IP position.

Status and next steps

Active engineering. Reference target boards under evaluation across the three FPGA families above, with selection driven by LVDS lane count, available block-RAM for the per-decoder FIFOs, and sideband I/O voltage compatibility with the discrete decoder ICs in the reference bench. Honest disclosure: no public release of reference RTL has been made at the time of writing. Expected release is gated on Trinity non-provisional drafting (target 2027-02-19 PCT deadline) and counsel review of any published RTL for SEP exposure, given the AOMedia AV2 and adjacent standardization tracks where Trinity sideband synchronization may surface as standard-essential.