TsugiSilicon
Hardware engineering. Multi-stream HDR pipelines, hardware-aware compression, and the silicon that ships in front of the viewer.
TsugiSilicon is the lab where the algorithms hit physical decoders, FIFOs, PLL trees, and consumer-class SoCs. Output is reference designs, FPGA bring-up notes, measured-data exhibits, and provisional patent disclosures positioned for AOMedia AV2 and adjacent standardization tracks. The thesis underneath: resolution-layering and obfuscated dual-layer compression have a clean freedom-to-operate window opening as the foundational 1990s-era patents from Demos, Demografx, and the early Dolby Vision predictive-encoder cluster have expired or expire through 2026, and TsugiSilicon's two filed provisionals stake additive-only and obfuscated-split positions in that window.
Research lines
- 01. TrinityPlesiochronous multi-decoder video synchronization
FPGA-scale sideband VBI extension, scanline-accurate additive composition across three fidelity-partitioned streams. App. 63/987,139.
- 02. DLCKeyed dual-layer compression with non-viewable layers
Pre-encode pixel-domain three-component obfuscation; on-SoC dual hardware decoder orchestration. App. 64/054,446.
- 03. TsugiNodeEdge hardware for cinema-grade playback
Off-the-shelf consumer SoC paired with the Trinity decode pipeline and the DLC dual-decoder, integrated end to end. In development.
- 04. FPGA bring-upReference designs for low-latency decode
Open reference RTL and bring-up notes for the synchronization fabric on commodity FPGA boards. The shortest path from datasheet to a working pipeline.
- 05. HW quantizationHardware-aware quantization for on-device decoders
Bit-depth schedules and dequantization layouts tuned for the actual memory hierarchies on shipping consumer silicon, not the textbook abstraction.
Mechanism overview
Two filed provisionals carry the lab's current technical thesis, operating at different scales of the same resolution-layering problem. Trinity (App. 63/987,139) addresses the FPGA-and-discrete-IC scale. A digital logic device hosts per-decoder asynchronous dual-port FIFOs (sized to several scanlines), a hysteretic watermark comparator, and a physically separate sideband signaling path that phase-locks plesiochronous discrete decoder ICs by commanding them to extend their vertical blanking interval when associated FIFO fill exceeds a high watermark. The output is scanline-accurate additive pixel-domain composition with saturating arithmetic across three fidelity-partitioned streams (base, color delta, gray delta). Additive-only reconstruction, distinct from the predictive-encoder approach in the Dolby Vision Profile 7 ecosystem.
DLC (App. 64/054,446) addresses the consumer-SoC scale. A pre-encode pixel-domain transform composes three keyed components (key-seeded tile permutation that preserves within-tile correlation, GoP-granular polarity inversion, and integer-root-of-unity chroma-axis rotation) and splits a high-precision master into two complementary streams such that no single layer is visually intelligible. Aggregate compression-efficiency cost lands in the low-double-digit-percent range against an unobfuscated split, versus near-total loss for naive visual cryptography. The decoder side orchestrates two concurrent hardware decoder contexts on a single consumer SoC under a shared PLL clock tree, with PTS-paired buffer matching and a proportional-control software throttle on the leading session. The same coordination problem Trinity solves with hardware sideband at the FPGA scale, solved with software-throttled rate control at the on-SoC scale. Hardware playback is verified on Amlogic S922X-J (Ugoos AM6B+).
Standardization track
The lab's primary standardization vector is AOMedia, with an engagement window targeted for 2026-08-01 (ninety days post-DLC filing). Promoter-tier membership is the current recommendation. AV2 specification work remains in draft as of May 2026, and the year-end-2025 launch did not complete on schedule, so the window favors a secure-transport-profile addendum positioning aligned with the AV2 12-bit professional tier. The strategic premise is that AV2 codecs will eventually want a distribution-side obfuscated dual-layer container for premium HDR content, and DLC's keyed pixel-domain pre-encode is one of the few candidate mechanisms that preserves codec-internal compression efficiency rather than fighting it. Counsel sign-off on standard-essential-patent scope is a precondition before any working-group contribution.
Counsel posture and commercialization horizon
Same prosecution counsel for both filings. Trinity twelve-month conversion and PCT deadline 2027-02-19. DLC twelve-month conversion and PCT deadline 2027-05-01. Track One Prioritized Examination at non-provisional filing recommended for both, to secure final disposition before the 2030 commoditization horizon for resolution-layered HDR distribution. PCT geographic scope decision targeting JP, KR, CN, and EU. For DLC, the open-issue list flags software-throttled rate control as a potential KSR-style obviousness risk against the Trinity sideband mechanism (counsel review at non-provisional drafting), and a measured-data exhibit is queued to strengthen the otherwise-constructive working examples ahead of Track One conversion.