TsugiFabric
The system-architecture lab. The substrate connecting algorithms to silicon: distributed training synchronization, compute fabric for adaptation workloads, and cross-domain co-design from decode to display to inference.
Algorithms move faster than silicon and silicon moves faster than the protocols that bind them together. TsugiFabric exists at that joint. Infinity, the lab's anchor patent, treats inter-accelerator timing as a first-class hardware primitive at nanosecond latency rather than a queue-management problem at microsecond latency, which is the layer where every pluggable-accelerator multi-vendor compute pool currently bottlenecks. Each subsequent work in the lab extends that substrate outward toward edge-class adaptation workloads, vendor-neutral signaling, and heterogeneous memory pools.
- 01
Infinity: Synchronization Substrate for Distributed Training
Patent pendingSideband phase-correction across pluggable accelerators with elastic gradient buffering. Filed US Provisional 64/055,093.
- 02
Compute Fabric for Edge AI Workloads
ResearchDistributed compute mesh for adaptation workloads that are too large for a single edge box and too small to justify a datacenter contract.
- 03
Cross-Domain Co-Design: Decode-to-Display-to-Inference
ResearchThe thesis-level integration question. Where do compression, training, and inference boundaries align such that the same silicon serves all three.
- 04
Sideband Synchronization Protocol for Multi-Vendor Pools
ResearchVendor-neutral phase-and-clock signaling between accelerators in a pluggable fabric. Designed for the rented-pool case, not the captive-rack case.
- 05
Pluggable Memory Pooling for Distributed AI Workloads
ResearchCXL-style memory aggregation across heterogeneous nodes, with allocation policies tuned for the activation-tensor traffic that AI workloads actually generate.
Plesiochronous gradient consensus
Infinity, the lab's anchor apparatus, composes four primitives. A White Rabbit (IEEE 1588-2019 HA) endpoint disciplines a per-node free-running oscillator at sub-nanosecond accuracy across kilometers of OS2 fiber. An FPGA elastic gradient-tensor buffer absorbs cross-node drift at gradient-tensor granularity, with hysteretic-watermark occupancy monitoring. A phase-correction sideband, electrically distinct from the high-speed serial data interface (preferred embodiment: PCIe Vendor Defined Message), closes the loop by throttling the source compute node's gradient publication rate. A CXL.mem pool indexed by a 64-bit regime identifier (epoch counter plus quorum hash) holds a bounded weight-snapshot retention pool with deterministic eviction, downstream of a parallel-popcount sign-quantized majority-vote consensus circuit. A WR-clocked watchdog timer decoupled from the epoch counter renders graceful degradation deadlock-free.
The deliberate apparatus-to-software mapping is the connective tissue between TsugiFabric and TsugiAI. K-Pool LoRA, filed as US Provisional 64/060,315, instantiates the same four primitives at the LLM software layer: a fixed-size pool of LoRA adapter snapshots (the bounded retention pool), a sign-quantized momentum optimizer over the active slot (the popcount-equivalent update), a gradient-detached content-aware routing module (the regime-identifier read path), and a fragility-aware retention policy (the deterministic-eviction analog). Freedom-to-operate from either filing to the other is structurally clean. The two patents form the apparatus and method ends of one continual-learning thesis.
UALink Consortium engagement, target 2026-07-30
Ninety-day post-Infinity-filing engagement window. Contributor-tier membership is the founder recommendation, conditional on counsel sign-off on the standard-essential-patent scope-limitation language. The architectural alignment is direct: UALink Common Specification 2.0's May 2026 update introduced in-network compute support, and Infinity's gradient-consensus circuit fits cleanly inside that surface as a fabric-side function rather than a host-side one. The consortium's preference for vendor-neutral hardware primitives matches the multi-vendor pluggable-pool framing of the patent. Contributor-tier first-year cost is on the order of twenty-five thousand dollars, set against a parallel non-provisional prosecution path so the apparatus claims continue to issue while the standardization track runs.
Infinity converts at the twelve-month deadline of 2027-05-01 with a Patent Cooperation Treaty filing. Track One Prioritized Examination is recommended alongside the PCT, with claim count limited to four independent and thirty total claims to comply with Track One. The same apparatus-prosecution counsel that handled Trinity, with familiarity with the Ex parte Desjardins 35 USC Section 101 safe-harbor framework, is the right pairing for non-provisional drafting on Infinity. Exhaustive freedom-to-operate sub-search across the hyperscaler-specific interconnect cluster (NVLink, NVSwitch, SHARP, ConnectX-8, Spectrum-X, NVLink doorbell registers, AWS Nitro virtual channels) is the blocking item before the non-provisional drafts. Output on this page is informational and is not legal advice; any filing-bound artifact should be reviewed by qualified patent counsel.