Lab

TsugiAI

The algorithms lab. Continual learning, signal-quantized optimization, and the parts of model behavior that survive contact with constrained hardware. Output is methods, ablations, and write-ups.

TsugiAI exists because the algorithms that work in a datacenter rarely survive the trip to the device a viewer actually owns. The lab pursues continual fine-tuning under hard no-replay constraints, optimizers whose per-step cost scales linearly in problem dimension rather than quadratically, and adaptation primitives whose memory and traffic profiles match the silicon they ship on. Three of the lab's active works are covered by filed US provisional patents, and the continual-learning and distributed-training lines ship as open-source SDKs (pip install tsugi).

Research lines

Five active works.

Each line is either filed as a US provisional patent, in active development with internal benchmarking, or in earlier-stage research framing. Status chips are conservative.

Continual Learning Without Catastrophic Forgetting Patent pending

A K-snapshot LoRA pool over a frozen pre-trained LLM, with a gradient-detached Gaussian-mixture router on a frozen sentence-transformer feature space and a sign-quantized optimizer applied only to the active slot. Filed as US Provisional 64/060,315 on 2026-05-07. The active research line under this work is the upper-bound oracle gap on sequential domain learning under a hard no-replay constraint, the regulated-data setting where rehearsal buffers are not legally available.
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Signal-Quantized Optimization for Edge Inference Patent pending

Sign-of-momentum updates on adapter parameters, plus the renormalization-derived optimizer family: MRRO (multi-resolution renormalization with deterministic inverse-RG refinement, Application 64/060,392) and CMLGS (one-dimensional coupled-map-lattice gradient smoothing at O(D) per step, Application 64/060,404). Both filed 2026-05-07. The thesis is that non-convex objectives with regular spatial structure or periodic topology admit per-step costs an order of magnitude below covariance-adaptive baselines, and that the gradient signal a constrained device actually needs is closer to a sign than a float.
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Adaptation Methods for Foundation Models on Constrained Hardware Patent pending

Parameter-efficient fine-tuning targeted at hardware below datacenter scale: phones, edge boxes, single-GPU workstations. The line covers adapter pool topologies, slot eviction policies under fixed parameter budgets, and the empirical question of which adaptation primitives survive once activation memory and KV-cache traffic are the dominant constraints rather than FLOPs.
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Routing Strategies for Mixture-of-Experts on Edge Silicon Research

Expert-selection policies that respect on-die memory layout and activation-tensor traffic patterns. Routing is treated as an optimization problem in its own right rather than a soft-attention afterthought. Open questions: gradient-detached versus jointly-trained gates under the regularized-data and on-device-personalization regimes, and the relationship between routing entropy and adapter-pool fragility.
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Calibration of Generative Models for Cinema-Grade Output Research

Color, motion, and frame-rate fidelity targets for video-generative models intended to share a delivery pipeline with traditionally captured cinema. The cross-pillar question for this lab: where do calibration constraints feed back into adapter selection, and where do they sit downstream of the decode and display chain owned by TsugiSilicon.
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Mechanism

Two intersecting research stacks.

The TsugiAI thesis is the deliberate composition of two stacks. The first is a continual-learning architecture: a fixed-size pool of K LoRA adapter snapshots over a frozen pre-trained LLM, with a gradient-detached content-aware router operating on a frozen sentence-transformer feature representation (Welford-fitted diagonal Gaussian mixture, never updated by the language-modeling gradient). Slot opening uses a bootstrap-and-novelty rule with a deterministic claim window; eviction at K-saturation prefers slots with the smallest batch count, a fragility-aware policy. Active-slot updates use sign-of-momentum on LoRA parameters only. The architecture is the deliberate software analog of the bounded weight-snapshot retention pool in the Infinity hardware substrate (Application 64/055,093).

The second stack is the renormalization-derived optimizer family. MRRO applies a renormalization-group-derived smoothing operator T from a parametrized family at a finite descending schedule of scales, with warm-starting between scales and a deterministic inverse-renormalization refinement at the terminal scale. The unified operator-T family includes three preferred embodiments under a common scheme: a frequency-domain low-pass cascade, a Gaussian convolution with Monte Carlo estimator, and a Kadanoff-Wilson block-decimation flow operator adapted from spin-lattice physics to continuous-objective optimization. CMLGS is the O(D)-per-step companion: a one-dimensional coordinate-aligned coupled-map-lattice diffusion chain on fixed-magnitude perturbation directions, with chaos modulation, error gating, and geometric annealing of the perturbation scale all explicitly excluded from the independent claim and recited only in dependent claims with workload-dependent operability honestly disclosed.

The two stacks intersect at the optimizer interface. The K-Pool LoRA active-slot update is sign-quantized today; the operator-T descending-scale schedule and the CMLGS coupled gradient estimator are candidate inner-loop replacements for the regimes where sign quantization underperforms. The empirical hypothesis being tested is that adaptation on constrained hardware is best served by composing a coarse routing decision with a per-slot optimizer whose per-step cost is independent of model dimension, rather than by a single jointly-trained network responsible for both.

Empirical highlights

Two figures from the patent record.

Figures reproduced from the filed-provisional record. Specific empirical multipliers are held back from public-facing surfaces; the K-Pool LoRA learning-rate plateau extent and the CMLGS dimensionality-scaling shape are the two most load-bearing public claims.

K-Pool LoRA learning-rate dose-response curve. Mean average forgetting on a five-domain sequential benchmark plotted against learning rate, showing a plateau across approximately 1.6 decades of learning rate followed by a deterministic first-task fit failure cliff. — K-Pool LoRA learning-rate plateau. Source: filed provisional 64/060,315, learning-rate dose-response audit (n equals 5 seeds, two scales).

Log-log plot of CMLGS residual versus problem dimensionality D in the set {10, 30, 100, 300, 1000, 5000} for Rastrigin-class objectives, with comparator curves for CMA-ES and AdamW. — CMLGS dimensionality scaling on Rastrigin-class objectives. Source: filed provisional 64/060,404, Working Example 1.

Counsel posture

Conservative on multipliers; specific on dates.

All seven filed provisionals in the parent portfolio are scoped for counsel review before non-provisional conversion. Joint-inventor assignment instruments for MRRO and CMLGS are in progress, with USPTO recordation under 37 CFR 3.11 ahead of the 2026-08-07 deadline. Twelve-month conversion and PCT decisions on K-Pool LoRA, MRRO, and CMLGS all fall on 2027-05-07. Specific empirical multipliers are held back from this surface. The portfolio's commercial assessment is maintained internally and shared in diligence.